1. Field of the Invention
It is related to a semiconductor wafer and a method of testing the same.
2. Description of the Related Art
These years, an increasingly wide use of portable electric appliances as well as an increasingly strong request for energy savings and reduction of industrial waste has intensified a demand for semiconductor devices, which include a non-volatile memory in which data is capable of being rewritten, and which retains data even when the power supply is turned off.
Examples of non-volatile memories include an EEPROM (Electric Erasable Programmable Read Only Memory) and a FeRAM (Ferroelectric Random Access Memory). Examples of a test to be carried out after completing these memories include an electrical test (retention test) for checking on whether or not data disappears after heating these memories up to a predetermined temperature. In some cases, this electrical test may be carried out after sealing a memory in a plastic package or after the assembling step. However, the test is usually carried out at the wafer level in order to classify non-defective chip and defective chip, since the wafer level testing can be carried out at higher temperature for a short time with low cost.
A result of the wafer level testing is visible in the form of a wafer map. Then, in a post-process, only non-defective chips are selected from the wafer based on the wafer map, and defective chips are discarded.
If, however, the semiconductor wafer is not aligned with the testing equipment, some inconveniences arise. For example, when the test is intended to perform on the chip A, chip B adjacent to the chip A might be unsuccessfully tested, so that non-defective chip and defective chip might be confusedly mishandled. If this is the case, defective chips are handled as non-defective chips in the post-process, or non-defective chips might be discarded as defective chips.
To deal with this problem, it is necessary in the wafer level testing to precisely grasp the location of semiconductor chip to be tested in the semiconductor wafer by, for example, aligning the semiconductor wafer and test equipment, while forming the reference mark formed in the particular region of the semiconductor and using the reference mark as a clue.
In the conventional example disclosed in Japanese Patent Application Laid-open Publication No. 2003-7604 (hereinafter referred to as “JPA No. 2003-7604”), a test is carried out by using a “process assessment pattern” formed in a particular position in a semiconductor wafer as the clue.
However, this method brings about such a problem that a region available for product chip is reduced by the region for the “process assessment pattern”, so that process cost for manufacturing the semiconductor device increases.
Another method of locating the chip to be tested in the semiconductor wafer is to count the number of chips from a periphery of the semiconductor wafer. However, a counting error is likely to take place in this method.
Taking these into consideration, JPA No. 2003-7604 is disclosing that, as shown in its FIG. 3, an exposure is carried out while a part of the reticle is intentionally covered with a shutter, and thereby an unfinished pattern is formed in a semiconductor chip which is used as a reference. According to this method, the unfinished pattern electrically insulates a bonding pad from a testing needle. Therefore, a voltage value of the semiconductor chip used as the reference becomes higher than a voltage value of any neighboring semiconductor chip, when read by use of the needle. In JPA No. 2003-7604, the chip used for the reference is distinguished from the neighboring chips.
However, this method brings about such a new problem that the unfinished pattern peels off from the wafer and generates particles, so that yield of the semiconductor chip reduces.
Besides the above-described methods, a method called as “drop shot” is sometimes used to form the reference mark for alignment in the semiconductor wafer. The “drop shot” is a method of making a contrast between a specific region (reference region) and neighboring regions. Such a contrast can be made by, for example, by intentionally getting rid of a part of a pattern in a product chip in the specific area (reference area) in a semiconductor wafer, or by forming a pattern different from those of the product chips in the specific region. When the testing equipment recognizes the difference of the contrast as an image, relative position between the reference area and the testing chip can be recognized, so that chip location in the semiconductor wafer can be grasped.
However, even in the case where the “drop shot” is used, since the pattern different from the product chips is formed in the reference region, the number of the chips that can be dicing out from the semiconductor wafer is reduced, so that the manufacturing cost for the semiconductor device is raised. Furthermore, when the “drop shot” is employed, stacked structure of the films becomes different between the reference region and other region, so that films in the reference region might peel off in some etching conditions.
In addition to JPA No. 2003-7604, Japanese Patent Application Laid-open Publication No. 2003-304098 and Japanese Patent Application Laid-open Publication No. 2002-83784 disclose some techniques relevant to the present application.